This application claims the priority of Application No. 2000-144371, filed May 17, 2000 in Japan, the subject matter of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a clock abnormality detecting circuit for detecting a frequency abnormality state (due to dropout and redundancy) of an externally inputted clock pulse by using an oscillator in a digital communication device (for example, a transmission device).
2. Description of the Related Art
Japanese Patent Laying-Open Publication Kokai No. H06-204993 (hereunder referred to as a first literature) and Japanese Patent Laying-Open Publication Kokai No. H08-316946 (hereunder referred to as a second literature) disclose conventional circuits for detecting clock abnormalities, especially, clock interruptions. Hereinafter, the conventional circuits disclosed in FIGS. 1 to 3 of the first literature and FIGS. 1 and 6 to 8 of the second literature are briefly described.
First, the conventional circuit employing a monostable multi-vibrator sets a time constant, which is determined by a capacitor C and a resistor R, and provides a pulse a having a pulse width with a value that is larger than the period of a subject clock signal. Thus, as long as the clock signal is inputted thereto, an output value of the multivibrator is maintained at one level, for example, at a high potential level (hereunder referred to H-level). At the suspension of a clock signal, the output value is changed to a low potential level (hereunder referred to as L-level). In the case of such a kind of a circuit, when the output value of the multivibrator is at L-level, it is determined that the clock signal is in an interrupted state.
Further, another conventional circuit having two counters is configured so that a clock signal subject is inputted to one of the counters, while a reference clock signal is inputted to the other counter, and that outputs of the counters are monitored by a comparator. In this case, the comparator monitors a counting-up operation performed in the counter and measures intervals, at which the counting-up operation is performed, according to a count value outputted from the latter counter. Incidentally, in the case that the counting-up operation is not performed for a certain time, it is determined that the former clock signal is suspended.
Moreover, another conventional circuit is configured in such a way as to use subject clock signals as reset signals and have a counter, which is connected and adapted to count reference clock signals, and to generate an output, which indicates the suspension of the subject clock signals, when a predetermined number of reference clock signals are inputted thereto during the interruption of the subject clock signals.
Furthermore, the detection of interruption of clock signals is performed mainly by the following conventional methods. That is, one of such conventional methods comprises the step of monitoring a subject clock signal every constant period by using a monitoring clock signal in the case that the monitoring clock signal is asynchronous to the subject clock signal and that the monitoring clock signal and the subject clock signal are inputted at the same rate, and the step of determining, when subject clock signals are not inputted thereto in the constant period at all, that the interruption of the clock occurs. Another conventional method comprises the step of detecting an edge of a subject clock signal in the case that the monitoring clock signal is asynchronous to the subject clock signal and that the subject clock signal is inputted at a rate lower than a rate at which the monitoring clock signal is inputted, and the step of determining, when a cycle of detection of an edge of the subject clock signal is longer than a preset value, an occurrence of the interruption of the clock signal. Still another conventional method is to configure a detection circuit in such a way as to comprise a frequency dividing means for generating, when interruption of a subject clock signal, which is asynchronous to a monitoring clock signal and inputted thereto at the same rate as a rate at which the monitoring clock signals is inputted, is detected, n series of frequency divided subject clock signals, whose change points are sequentially shifted by dividing the frequency of the subject clock signal by n, and a clock interruption detecting means for detecting the presence or absence of a change point of the frequency divided subject clock signal by using the monitoring clock signal and for sensing interruption of the subject clock every duration of a monitoring control signal according to a result of detecting the presence or absence of a change point.
The aforementioned conventional methods, however, have the following disadvantages or drawbacks.
That is, the conventional methods have, for example, a drawback in that the capacitor C and the resistor R to be added to the multi-vibrator render the detection circuit unfit for integration thereof. Moreover, the. conventional method of determining the suspension of the clock signal by making comparison between outputs of the counters enabled to operate independent of each other according to two asynchronous clock signals has drawbacks in that the internal configuration of the comparing circuit is extremely complex, and that the comparing circuit lacks precision.
According to a first clock abnormality detecting circuit of the invention, a shift register is used for detecting abnormalities in a subject clock signal. It is determined according to data, which represents a result of sampling of a monitoring clock signal according to the subject clock signal and is outputted from each of the columns or stages of the shift register, whether or not the subject clock signal is normal. Thus, the number of change points is reduced. Consequently, the gate size of the clock abnormality detecting circuit is decreased. Moreover, the power consumption thereof is lowered.
According to a second clock abnormality detecting circuit of the invention, similarly as in the case of the first clock abnormality detecting circuit, a shift register is used for detecting abnormality of the subject clock signal. It is determined according to data, which represents a result of sampling of a monitoring clock signal according to the subject clock signal and is outputted from each of the columns or stages of the shift register, whether or not the subject clock signal is normal. Thus, the second clock abnormality detecting circuit has advantageous effects similar to those of the first clock abnormality detecting circuit.
Even in the case of the third clock abnormality detecting circuit of the invention, which is obtained by reversing the relation between the monitoring clock signal and the subject clock signal in the first or second clock abnormality detecting circuit of the invention, advantageous effects similar to those of the first or second clock abnormality detecting circuit are obtained.
In the case of the fourth clock abnormality detecting circuit of the invention, which has a normal value detecting circuit, which is operative to detect a normal output state in accordance with an output state of each of the columns of the shift register, and an abnormal value detecting circuit, which is operative to detect in accordance with the output state of each of the columns of the shift register an abnormal clock input value that exceeds the value indicated by a normal input, as abnormality evaluation circuits for the first, second or third clock abnormality detecting circuit of the invention, the most fundamental circuit configuration is realized.
In the case of the fifth clock abnormality detecting circuit having a plurality of normal value detecting circuits, which differ from one another in conditions for regarding a state as a normal one and are operative to detect a normal state in accordance with output states of each of columns of the shift register, a storage means for storing one of results of detection performed by the plurality of normal value detecting circuits and an abnormal value detecting circuit for detecting an abnormal clock input value that exceeds a normal input value, as components of one of the abnormality evaluation circuits of the first, second, or third clock abnormality detecting circuit of the invention, and also having a plurality of normal value detecting circuits, which differ from one another in conditions for regarding a state as a normal one and are operative to detect a normal state in accordance with output states of each of columns of the shift register and which are adapted so that only the normal value detecting circuits directed to a detection of a normal output state on a condition differing from the conditions for regarding a state as a normal one according to a result stored in the storage means provided in the one of the abnormality evaluation circuits, and an abnormal value detecting circuit for detecting in accordance with an output state of each of columns of the shift register an abnormal clock input value that exceeds a normal input value as components of the abnormality evaluation circuit other than the one of the abnormality. evaluation circuits thereof, the configuration of the circuit dealing with the case, in which a plurality of normal states are present, is realized.